The present invention generally relates to the field of buffers, and particularly to a buffer improvement suitable for higher operational speeds.
Modern life has made great advances helped through the provision and improvement of electronic devices. From the provision of information handling systems, such as desktop computers, servers, mobile computers, Internet appliances, convergence systems, and the like, to other electronic devices encountered by a user, these devices have a profound effect on most every aspect of a user""s life. Competition of manufacturers and assemblers of electronic devices and components has made improvements to the speed and efficiency of these systems desirable to increase both the functionality and competitive advantage of the device.
Improvements to components in an electronic device may be greatly magnified based on a speed-up achieved when multiplied by the massive number of operations performed by electronic devices. For example, buffers, which may include an isolating circuit, often utilizing an amplifier, used to minimize the influence of a driven circuit on a driving circuit, may have a significant propagation delay. This propagation delay was generally necessary to delay turn on and off output buffer stages for noise reduction in the buffer. However, this delay may significantly slow a circuit when the delay is multiplied over the vast number of operations performed utilizing the buffer.
Therefore, it would be desirable to provide a buffer improvement for higher speed operation by decreasing the propagation delay of the circuit.
Accordingly, the present invention is directed to a buffer improvement for higher speed operation. In a first aspect of the present invention, a buffer includes at least two buffer stages, which may include a first buffer stage and a second buffer stage. A voltage conversion circuit is disposed between the first buffer stage and the second buffer stage. The voltage conversion circuit is suitable for acting as a delay between the first buffer stage and the second buffer stage. In this way, the voltage conversion circuit may be used in place of inter-stage resistors to provide a decrease in the propagation delay of the buffer.
In a second aspect of the present invention, a buffer includes a first buffer stage driven directly from at least one of an internal supply and an external supply. A second buffer stage is also included, with a voltage conversion circuit disposed between the first buffer stage the second buffer stage. The first buffer stage is driven at a first voltage level from the at least one of the internal supply and the external supply, and the second buffer stage is driven at a second voltage level, the second level corresponding to an output of the voltage conversion circuit.
In a third aspect of the present invention, a buffer includes at least two buffer stages, which may include a first buffer stage and a second buffer stage. A means for converting voltage from a first voltage level to a second voltage level is disposed between the first buffer stage and the second buffer stage. The voltage conversion means is suitable for acting as a delay between the first buffer stage and the second buffer stage.
In a fourth aspect of the present invention, a buffer includes a first buffer stage driven direction from at least one of an internal supply and an external supply. A second buffer stage is also included. The first buffer stage is driven at a first voltage level from the at least one of the internal supply and the external supply, and the second buffer stage is driven at a second voltage level.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.